Many types of current semiconductor devices, such as complex programmable logic devices (CPLDs), have multiple voltage sources or supplies (e.g., 3.3V and 5V) to power different portions of the device. For example, with voltage rails supplying two different voltages, a control mechanism is needed to control the order, timing, ramping, and voltage differential in which the rails are powered up and down. This is commonly known is power-sequencing. Without proper power-sequencing, the device can be subject to short-term failures or malfunction. For example, improper sequencing can damage portions of the device by mechanisms known as latch-up or cause false initialization of device portions, such as memory or logic circuits.
To address this general problem of power-sequencing, dedicated devices have been developed specifically suited to perform the controlled sequencing of several power supplies. These are referred to as power-sequencers. However, as sequencing requirements for boards requiring many power supplies or power supply areas become increasingly more complex, a single power-sequencer device may no longer be able to meet all the system or user needs. Even though each power-sequencer may be highly programmable in both characteristics and functionality, the actual needs in any given power-sequencing application may exceed the capabilities of any of those devices. In these cases, connecting multiple devices together can increase the functional capabilities and allow more complex functions to be implemented. In some applications, large numbers of power supplies, e.g., 12 or more, may have to be monitored and controlled on a board, such as properly sequenced generation of Enable signals for power supplies, LDOs (low drop out voltage regulators), or power FET (field effect transistor) switches. As a result, multiple devices assigned to handle the complex power-sequencing process may be required.
In those cases, problems generally arise during power-up or power-down sequences since each power-sequencer device typically has its own protocol for supplying power during these operations with different electrical characteristics, including start times and ramping rates. Currently, both programmable and fixed devices exist to handle the power management process, such as during power-up or power-down. However, problems may arise when combining these devices to handle complex power-sequencing needs. For example, during a power-up (or wake-up) phase, control signals to multiple power supplies, LDOs or power-FETs may be improperly or unintentionally released.
Such undesired wake-up results are due in part to the finite time required for each of the devices to assume their internal configuration, establish all internal operating points, and begin proper operation. That finite wake-up time varies due to manufacturing tolerances, making it necessary to synchronize the actual start of the overall sequencing process. It is also conceivable that other devices (e.g., third-party supervisory and monitory ICs, either fixed or programmable) would participate in the overall power-supply monitoring and sequencing process, making it desirable to allow for synchronization of all devices involved. Thus, a method that inhibits the release of any control signals which could potentially turn on various power supplies and thereby harm or destroy the electronics connected to those supplies is desired.
Furthermore, since power supply monitoring and sequencing is highly critical to the robust operation of the entire system which these power supplies feed, the sequencers for both single and multiple devices should be able to withstand harsh operating conditions (e.g., large transitions in supply voltage).
Accordingly, it is desirable to have a robust power-sequencing method for multiple devices that is not prone to false synchronization and premature assertion of operational signals.